Samsung's three-step plan to put memory directly on top of AI chips

The bottleneck in AI training is no longer how many GPUs a buyer can find. It is how fast the chip next to the GPU can pull data from the memory stacked above it. At Hot Chips 2026, Samsung's DRAM Design Team put a name to the fix it is building toward: a three-phase path that makes the HBM base die smarter before the memory is glued directly on top of the AI accelerator.

HBM, or high bandwidth memory, is the stack of DRAM dies that sits next to an AI chip. Inside that stack, the base die (the layer at the bottom) is mostly a passive interface today. It relays signals between the compute die and the DRAM cells stacked above it, through vertical wires called through-silicon vias (TSVs). As AI models have grown, that base die has become the wall. Adding more TSVs means cramming them closer together; shrinking the pitch raises signal-integrity headaches; and the physical-layer interface (PHY) that actually moves data in and out is running out of I/O power and area.

Samsung's answer, presented by its DRAM Design Team at Hot Chips and laid out at FMS 2026 earlier in August, is a named three-phase sequence: CHBM, then AHBM, then zHBM.

The first step, CHBM (Custom HBM), moves the base die from DRAM-process silicon to an advanced logic node. Today's HBM4 already ships with a 4nm logic base die plus Samsung's D1c DRAM process. The point of CHBM is to give the base die room to host real logic, not just passive relaying. Once the base die is a logic chip, it can do more than pass data through.

That is what AHBM (Advanced HBM) does. AHBM takes the logic that CHBM enabled and expands it beyond a vanilla PHY, adding functional blocks that would have lived on the AI accelerator's package before, including customer-specific work. Samsung describes this as making the base die an "intelligent partner" to the compute die. The practical effect: more of the interface work moves off the AI chip and onto the memory stack beside it.

The third step, zHBM, is the one the wccftech recap covered as a standalone story. Here the DRAM stack sits directly above the AI accelerator (the compute die) using wafer bonding and a customer-specific interlayer that lets Samsung integrate each customer's IP. The numbers Samsung is targeting, stated as forward-looking projections rather than measured benchmarks, are roughly 8x interface performance and greater than 10x memory density versus HBM5, 3x energy efficiency, and a greater than 50% drop in thermal resistance.

The bandwidth figures underline why the base die is the new frontier. HBM4 today delivers more than 3 TB/s per stack. HBM4E pushes that to roughly 4 TB/s. HBM5, the next node, is targeting more than 60 GB of capacity per stack and double HBM4's bandwidth. Hitting those numbers means pushing the base-die TSV count, TSV pitch, and PHY I/O harder than they have been pushed before, which is the wall Samsung's three-phase path is designed to take apart in order rather than all at once.

The base-die bottleneck is not unique to Samsung. The HBM interface has been a shared wall across the industry, and the move to logic-process base dies is one of several routes vendors are now testing. Adjacent ecosystem signals, d-Matrix's Raptor 3D-DRAM among them, are working on the same problem from the compute side, asking what happens when DRAM integrates with the accelerator rather than stacking beside it. Samsung's three-phase path is a memory-side answer to a question the rest of the industry is also asking.

Samsung paired the HBM roadmap with a parallel NAND announcement. V10 BV-NAND (Bonding V-NAND) crosses 400 layers using new wafer-bonding techniques, thirteen years after Samsung's first V-NAND shipped in 2013. zNAND-O, the 3D-stacked NAND counterpart to zHBM, ships in 4- and 8-layer versions aimed at edge AI inference.

What Samsung did not lay out at Hot Chips is the part that will decide whether the path lands. The three phases have names, target numbers, and a public conference stage; they do not yet have a shipping date, a product family, or a named customer accelerator. The next test of the roadmap is whether CHBM shows up in a real HBM part before zHBM's 3D stacking becomes the announcement everyone remembers.