Researchers ran a peer reviewed quantum optimization technique on Rigetti's 9 qubit chip that uses fewer physical qubits than a problem's variables normally require, with a tunable trade off in sequential operations the chip must perform.
Rigetti Computing researchers, in a peer-reviewed paper in Physical Review Applied, say they have run a quantum optimization technique on a 9-qubit superconducting chip that solves a standard hard-class benchmark, Sherrington-Kirkpatrick spin-glass models, using fewer physical qubits than the problem's classical variables would normally require. The work, reported by Quantum Computing Report and dated 2026-09-14, is a structural step, not a claim of quantum advantage.
The technique's core move is partitioning. Where a standard quantum optimization approach like QAOA (Quantum Approximate Optimization Algorithm) assigns one physical qubit per problem variable, Rigetti's variational approach groups the N classical variables into K groups of D bits each, encoding the problem configuration as a superposition across a smaller quantum state space. The hardware saving is built into the encoding, not borrowed from a hardware advance.
The cost shows up elsewhere. The technique trades qubit count for circuit depth: the number of sequential quantum operations the chip must perform. Because the partitioned encoding is less expressive per qubit, the algorithm needs more layers of operations to reach a usable answer. The team treats this as a tunable knob. A researcher with a small chip can run a shallower circuit on more variables; a researcher with a bigger chip can run a deeper circuit on fewer variables, choosing where to spend the hardware budget. A standard QAOA run does not give that choice.
Rigetti validated the approach end-to-end on its 9-qubit superconducting processor against Sherrington-Kirkpatrick spin-glass models, a long-standing benchmark family for hard classical optimization. The team also reported parameter concentration: optimal circuit parameters, once found for one problem instance, can be reused on similar instances without re-running the full classical tuning loop. That property matters because classical parameter optimization is the dominant overhead in variational quantum algorithms. It is the part of the run that happens on a regular computer, not the quantum part. A 2019 result by Farhi, Goldstone, and Gutmann established that QAOA parameters concentrate near fixed values as problem size grows, and Rigetti's earlier preprint on qubit-efficient optimization extended that line. The new paper pushes it onto real hardware.
The work was supported by DARPA and the U.S. Department of Energy's National Energy Research Scientific Computing Center (NERSC), the lab's classical-compute backbone for the parameter-tuning runs. Rigetti's technical write-up on Medium treats the result as a building block for early fault-tolerant hardware, not a present-day product capability.
The honest size of the demonstration is 9 qubits. That is enough to validate the encoding, the depth trade, and parameter concentration on a small problem class. It is not enough to claim that the technique beats classical solvers on real-world optimization at scale. Independent work has put pressure on the premise. An arXiv preprint on approximate spin-glass optimization at larger sizes finds no quantum advantage in the relevant regime, and a Nature npj Quantum Information study maps the practical scaling limits of heavy-hex QAOA, the layout Rigetti's chips use, on current superconducting hardware. The Rigetti team's claim is narrower. The encoding is qubit-efficient, the trade is tunable, and the parameters concentrate. Whether those properties translate into a real advantage at problem sizes classical machines struggle with is the next question, and it is not settled by a 9-qubit run.
The next signal to watch is whether other groups reproduce parameter concentration on the same encoding with different hardware, and whether the depth-vs-width knob holds up outside Sherrington-Kirkpatrick benchmarks. A larger demonstration on, say, a 30- or 60-qubit device would shift this from a structural technique to a candidate architectural choice for early fault-tolerant designs.