IBM Reveals Spyre Accelerator: A New Enterprise AI Inference Chip
# IBM Reveals Spyre Accelerator: A New Enterprise AI Inference Chip IBM has unveiled the Spyre Accelerator, a new AI inference chip built on a clean-sheet dataflow architecture designed for enterprise AI workloads. The Spyre SoC is implemented in 5nm CMOS and contains **25.6 billion transistors**.
IBM Reveals Spyre Accelerator: A New Enterprise AI Inference Chip
IBM has unveiled the Spyre Accelerator, a new AI inference chip built on a clean-sheet dataflow architecture designed for enterprise AI workloads.
The Spyre SoC is implemented in 5nm CMOS and contains 25.6 billion transistors. It features 32 active cores (plus 2 spares for yield) with a unique "corelet" architecture—each core is divided into two corelets containing 2D systolic arrays for matrix multiplication and 1D vector arrays for activation functions.
Key specs:
The chip is designed for integration with IBM Z and Power systems—up to 48 cards in an IBM Z or LinuxONE system, or 16 cards in IBM Power. The software stack is built on PyTorch 2.x, allowing applications to run "with essentially no software changes," according to IBM.
"Spyre is the result of a clean-sheet dataflow architecture AI accelerator concept," IBM noted, adding that while it's inference-optimized now, the architecture was designed with "future-proofing" to enable fine-tuning and training in later versions.
