AI inference moved the bottleneck inside the server. Imec is engineering the optical fix.

The AI infrastructure story used to be a GPU story. Training the largest models required more chips, more power, and more bandwidth between racks in the datacenter. Optical links already solved that scale-out problem. The bottleneck has moved.

Now the dominant workload is inference, the work of running a trained model for thousands of users at once. That changes the geometry of the traffic inside a server. Inference demands low, reactive latency for every response. It threads long context windows through retrieval-augmented generation, reasoning, multimodal inputs, and multi-agent flows, all of which keep memory and accelerator traffic high and sustained. The bandwidth that used to flow between racks now has to flow between chips and chiplets on the same board, which is where electrical interconnects begin to give way. As Peter Ossieur, imec's portfolio director and a Ghent University professor, told EE Times, that shift is what makes scale-up the new bottleneck.

The scale-up and scale-out distinction is the spine of the piece. Scale-out is the link between racks in a datacenter, a problem the industry solved years ago with pluggable optical transceivers that move data centimeters to meters at high speed. Scale-up is the connection inside a single server or rack domain, between GPUs, memory, accelerators, and switches that have to act like one computer. That traffic cannot tolerate the latency, signal loss, or reach limits of copper at the bandwidths the new inference workloads require. Imec has reorganized its optical interconnects program to treat that gap as the central research question: how do you put light close enough to the chip that electrical reach stops being the binding constraint?

The institute's answer is a portfolio, not a single trick. Imec runs an explicit silicon photonics research line tied directly to cloud datacenter and AI/ML networking bandwidth demand, tracking the integration and packaging changes needed to bring optical I/O out of pluggable modules and onto the package itself. The institute's program materials also list commercial partnerships with co-packaged optics players, including work with Celestial AI, an indication that hyperscaler-aligned vendors are already designing at this scale rather than watching from a distance.

Industry programming is moving on the same axis. Imec's ITF Japan 2026 agenda includes a dedicated session, "Optical interconnects powering future AI compute clusters", treating the inside-server optical fabric as a present engineering problem rather than a roadmap item. Operators and builders are doing the design work now, not waiting for the link budget to force their hand.

Packaging is where the mechanism gets concrete. Imec has demonstrated die-to-wafer hybrid bonding at a 2-micrometer copper pad pitch, a dense short-reach interconnect that has to coexist with optical I/O on the same package. Without that kind of bonding, signal integrity between the chip and the optical engine gives way, and co-packaged optics loses the density advantage that makes it worth wiring up in the first place.

The direction, not the market share, is what this evidence supports. Imec's portfolio treats co-packaged optics as the design shift that matches the scale-up bottleneck, not as a forecast of which vendor will ship the most units. Adoption volume and hyperscaler shipment figures are not in the public record, and the institute's own statements stop at program scope and demonstrated capability. The next data points to watch are whether ITF Japan surfaces named customer designs that put optical I/O inside the package rather than alongside it, and whether 2-micrometer hybrid bonding moves from imec's demo line into a foundry process window.